Semiconductor ICs are formed on a semiconductor wafer that is divided into a plurality of dice each being an IC device. The wafer is tested at different stages of manufacturing for defects to ensure the quality and yield of the ICs. The defects may be inherent in the semiconductor material of the wafer or may result from any step of the manufacturing. Depending on the type and location, a defect may cause an IC to fail, require some repair work of the IC, or be harmless. In some examples, the potential impact of a defect on the die loss depends at least partially on the potential use (or grade) of the IC. Some defects can be tolerated because of functional redundancy provided by design. Some defects can be corrected during the manufacturing process once they are detected.
Inspection and die loss prediction at various stages of IC manufacturing substantially reduces the cost of ICs. The cost of an IC includes the cost of testing at different stages as well as the cost to perform each step of manufacturing. Detection of failing dice potentially saves the cost for performing further manufacturing and test on parts that are known to fail. In addition, the detection of the defects and identification of the type of defect allows for a decision on whether the manufacturing process of a wafer or other wafers in the lot should be continued, terminated, or adjusted (for example, to allow repair of defects) following each step of wafer inspection. To make such a decision, the die yield is to be predicted after each step of wafer inspection. Wafer inspection tools that detect defects on wafers and identify the detected defects by various defect types are commercially available. What is needed is an analysis system that predicts the die loss for a wafer based on defects detected by a wafer inspection tool during each step of wafer inspection.